Design of an on-silicon-interposer multi-layered passive equalizer for next generation high bandwidth memory (HBM)

Abstract

High Bandwidth Memory (HBM) is a 3-dimensional memory on a silicon (Si)-interposer which provides high density and fine pitch design rules. With the help of 1024 I/O lines on a Si-interposer and 2 Gbps data rate per each I/O line of a HBM, 1 TB memory bandwidth could be achieved by 4 HBMs on an interposer. To increase bandwidth over 1 TB, however, inter-symbol-interference (ISI) which limits high-speed data transmission should be relieved by an equalizer. In this paper, we propose a new on-Si-interposer passive equalizer for next generation HBM with 1024 I/O lines and 8 Gbps data rate. The proposed equalizer consumes 2.32 mW, zero effective area, and provides 7 $\mu m$ fine pitch, which enable the equalizer to be applied to HBM with 1024 I/O lines. Robust performance that is independent of installation point provides design flexibility. The performance of the proposed equalizer is verified using simulation and fabrication. By applying the proposed equalizer, the eye-diagram which was completely closed without an equalizer is successfully open with eye-height of 11.5 % $V_{TX,output}$ and eye-width of 57.8 % UI at a bit error rate (BER) of 1E-12.