Fast timing simulation of custom digital circuits through HDL modeling

Abstract

We suggest methodology to estimate timing of custom digital design without slow SPICE simulation and logic verification methodology. Delay of logic gates that consists of transistors is different according to input vectors. We suggest method to estimate delay considering input vectors. To improve the accuracy of the propagation delay, we considered Miller capacitance. We applied the effective turn-on resistance of transistors which could be different due to the position of transistors. Also, we proposed the method can reduce the error of slew calculation compared to conventional slew calculation method, and we adjusted cell delay according to calculated slew. Due to the wire, delay can be added. We estimate the wirelength using the coordinate of cells and applied the propagation delay due to wire. Experimental result shows that the proposed timing simulation flow accelerated runtime about 500 times compared to SPICE simulation. Also, accuracy enhancement techniques reduced the error of delay estimation by 15\% averagely