VLSI architecture for turbo and LDPC convolutional codes터보 및 LDPC 컨볼루션 코드를 위한 VLSI 구조

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This dissertation proposes various methods and hardware structures for efficient decoding of turbo and LDPC convolutional codes. First, three studies have been conducted to resolve various bottlenecks of the turbo decoder used in the LTE-Advanced wireless communication standard. A novel decoding algorithm and its hardware realization are proposed to enhance the throughput of turbo decoding in LTE-Advanced systems. The proposed method called tail-overlapped decoding completely removes the undesired phase-switching latency by partially overlapping in-ordered and interleaved decoding phases, and as a result, achieves a significant increase of decoding throughput. Moreover, the algorithm does not degrade error-correcting performance for high-rate codes which are essential to achieve the maximum data rate of LTE-Advanced systems. A 3GPP LTE-Advanced turbo decoder supporting both of conventional and proposed decoding methods is implemented in $0.13- \mu m$ CMOS technology to show the effectiveness of the proposed algorithm. The decoder exhibits a decoding rate greater than 1Gbps with six iterations, meeting the peak data rate of the LTE-Advanced standard with much less hardware complexity than those of the previous works. In addition, a new structure for the extrinsic information memory in turbo decoders is proposed to eliminate memory contentions and reduce the hardware complexity. Since the extrinsic information memory has to deal with multiple accesses at the same time, conventional turbo decoders mainly employ dual-port memory with large area. However, by analyzing the interleaving rule defined in the LTE-Advanced standard, it is proved that extrinsic information can be stored only by single-port memory. As a result, the complexity of the extrinsic information memory is reduced by about 27% when using commercial on-chip memory. Also, this dissertation presents a reverse rate matching method for LTE-Advanced turbo decoders. In LTE-Advanced systems, the turbo codes are highly punctured to achieve high data rate when the channel is reliable. In that case, since only a small part of the input frame memory contains meaningful data, accessing all entries of the memory is redundant. To reduce the meaningless accesses, the proposed reverse rate matching method evaluates whether each code bit is punctured or not. As a result, more than 30% of the power consumed in accessing the input memory can be saved when the code rate is high. Furthermore, a low-complexity hardware architecture realizing the proposed method is presented for parallel-SISO decoding. By making use of a specific relationship resident in parallel input indexes, the hardware complexity of the reverse rate matching unit is reduced by 44%. Second, this dissertation proposes a low-power LDPC convolutional code decoder that is fully compatible with the IEEE 1901 standard. The proposed architecture merges multiple memory banks into one to make it consume much less power than the conventional architecture. Memory operations conducted by all the unit processors are synchronized in the proposed decoder to merge the memory and avoid any possible data hazard. The data hazard happens when a unit processor tries to read a log-likelihood ratio before a different processor updates it, degrading the error-correcting performance. Memory-access patterns appearing in a memory-based LDPC convolutional code decoder are formulated to determine the size of a sliding window adequate for decoding. Experimental results show that the decoding architecture employing the merged memory and the proper window size reduces the power consumption by up to 40% compared to the conventional architecture that employs multiple memory banks.
Advisors
Park, In-Cheolresearcher박인철researcher
Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2017
Identifier
325007
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2017.2,[v, 70 p. :]

Keywords

Error-correcting codes; Convolutional codes; Turbo codes; LDPC codes; VLSI decoding architecture; 오류 정정 부호; 컨볼루션 부호; 터보 부호; LDPC 부호; VLSI 복호기 구조

URI
http://hdl.handle.net/10203/242034
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=675832&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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