Development of process technology for high performance Ge MOSFETs = 단위 공정 연구를 통한 고성능 게르마늄 소자 개발

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Ge has a big advantage over Si in terms of high electron and hole mobilities, and its low processing temperature makes it easier to integrate with high-k materials. This dissertation presents two approaches to address issues of Fermi level de-pinning at the metal/n-Ge interface and the formation of reliable gate stack considering its thermal instability and electrical performances. In the metal/n+-Ge contact of Ge n-MOSFETs, there is a strong Fermi level pinning neat the valence band edge of Ge bandgap in the metal/Ge contact and this leads a high contact resistivity with high Schottky barrier height as same as its band gap. We demonstrated two kinds of Fermi level de-pinning methods which are the direct deposition of TaN on the Ge surface and self-aligned $Ti/GeO_2/Ge$ contact to form an interfacial $TiO_x$ thermodynamically. These two approaches reduce the Schottky barrier height for electron by a half of Ge band gap. In the gate stack, in order to overcome the limit of conventional thermal growth fabrication process, a plasma oxidation methodology has been purposed to form a $GeO_2$ channel passivation layer on the Ge surface. In addition, to suppress the $GeO_2$ desorption during/after the fabrication, $Y_2O_3$ and AlON capping layers are studied in the light of EOT scalability and gate stack quality. In the case of $Y_2O_3$ passivation, there is a certain scalability limitation below EOT of 1.0nm as a $GeO_2$ capping layer due to the introduction of high trap site density as $Y_2O_3$ thickness below 1.0 nm. AlON is the better choice for $GeO_2$ channel passivated Ge MOSFET with reliable device operation compared with conventional $Al_2O_3/GeO_2$ MOSFETs due to its lower border trap density than $Al_2O_3$.
Advisors
Cho, Byung Jinresearcher조병진researcher
Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2017
Identifier
325007
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2017.2,[x, 96 p. :]

Keywords

germanium; transistor; Fermi level pinning; gate stack; germanium oxide; yttrium oxide; aluminium oxynitride; 게르마늄; 트랜지스터; 페르미 준위 고정; 게이트 구조; 게르마늄 산화막; 이트륨 산화막; 알루미늄 산화질화막

URI
http://hdl.handle.net/10203/242022
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=675820&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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