(A) high-speed current-steering DAC design with a stacked unit cell for wideband linearity

Abstract

This work demonstrates a compact and low power wideband full binary DAC that reduces the circuit complexity by eliminating non-essential building blocks such as the binary-to-thermometer decoder and by utilizing the Stacked Unit Cell (SUC) structure instead of the traditional two-dimensional (2D) current source matrix. As a result of the recent advances in CMOS processes, the current source matching for a 6 bit DAC has become a non-critical design challenge. Thus, the circuit complexities from the popular common centroid 2D current source matrix and thermometer decoding seem to be unnecessary expenses

hence, they are deliberately removed in this work. By using identical unit slices in composing binary-weighted current sources, the code-dependent timing skew and the parasitic-induced output impedance reduction problems have been alleviated. For the application of the ultra-high-speed sampling rate such as wireless chip-to-chip communication, this work proposes a 6 bit 20 GS/s full binary 2-times interleaved current-steering DAC. For the design of low power and small area at the ultra-high-speed sampling rate, SUCs based 6 bit full binary architecture was used in the sub-DACs. To resolve the effect of the huge glitch in major-code transition and to guarantee the synchronization among the widely spread unit cells, a 2-times interleaving architecture was utilized. By the appropriate selection and the optimum design for the implementation of a path selector, this work reduced the hardware burden and used the single power supply of 1.2V. The prototype demonstrated stable performance for the entire range of signal frequencies at 20GS/s and showed the FOM comparable with that in the-state-of-the-art designs in 65 nm CMOS technology.