A Low-Reference Spur MDLL-Based Clock Multiplier and Derivation of Discrete-Time Noise Transfer Function for Phase Noise Analysis

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A multiplying delay-locked loop (MDLL)-based clock multiplier with a two-step phase aligning architecture and a dual-pulse charge-pump (CP) is proposed to reduce the reference spur level. The architecture has a phase-locked loop mode to align the coarse phase and an MDLL mode to obtain a delay-lock. With non-overlap dual phase detector pulses in the MDLL mode, the CP is directly calibrated in the runtime to minimize its phase offset. A discrete-time noise transfer function (NTF) is also derived to estimate the phase noise of multiplying-delay line from that of delay line. The NTF includes aliasing effect and shows better accuracy than the prior voltage controlled oscillator realignment-based approaches. This clock multiplier occupies an active area of 0.047-mm(2) in 40-nm CMOS process. The clock multiplication ratio (N) is an integer value from 8 to 27. With a low-cost 19.2-MHz TCXO reference, 153.6-518.4 MHz clocks were successfully generated, and a phase noise of -124 dBc/Hz at 100-kHz offset from a 518.4-MHz clock, rms jitter of 1.28 ps, and -65.5 dBc reference spur were measured. The power dissipation at 518.4 MHz was 2.6 mW from the 1.8 and 1.1 V supplies.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2018-02
Language
English
Article Type
Article
Keywords

CHARGE PUMP; LOW-POWER; PLL; DLL; INJECTION; OSCILLATOR; INTERFACE; CMOS

Citation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.65, no.2, pp.485 - 497

ISSN
1549-8328
DOI
10.1109/TCSI.2017.2719685
URI
http://hdl.handle.net/10203/240382
Appears in Collection
EE-Journal Papers(저널논문)
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