A compact multi-bit flip-flop with smaller height implementation and metal-less clock routing
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Seo, Jae-Woo | ko |
| dc.contributor.author | Jung, Jinwook | ko |
| dc.contributor.author | Shin, Youngsoo | ko |
| dc.date.accessioned | 2018-02-21T05:55:29Z | - |
| dc.date.available | 2018-02-21T05:55:29Z | - |
| dc.date.created | 2017-11-29 | - |
| dc.date.created | 2017-11-29 | - |
| dc.date.issued | 2018-02-28 | - |
| dc.identifier.citation | SPIE Advanced Lithography | - |
| dc.identifier.uri | http://hdl.handle.net/10203/240187 | - |
| dc.language | English | - |
| dc.publisher | SPIE | - |
| dc.title | A compact multi-bit flip-flop with smaller height implementation and metal-less clock routing | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.citation.publicationname | SPIE Advanced Lithography | - |
| dc.identifier.conferencecountry | US | - |
| dc.identifier.conferencelocation | San Jose Convention Center | - |
| dc.contributor.localauthor | Shin, Youngsoo | - |
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