A one DIvisionPer Clock Pipelined Division Architecyure Based on LAPR(Lookahead of Paetial-Remainder) for Low-Power ECC Applications

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Publisher
ISLPED
Issue Date
1997-08
Language
English
Citation

International Symposium on Low Power Electronics and Design, pp.220 - 224

URI
http://hdl.handle.net/10203/23989
Appears in Collection
EE-Conference Papers(학술회의논문)
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