DC Field | Value | Language |
---|---|---|
dc.contributor.author | 조규형 | ko |
dc.date.accessioned | 2017-12-20T12:48:18Z | - |
dc.date.available | 2017-12-20T12:48:18Z | - |
dc.date.issued | 2007-10-16 | - |
dc.identifier.uri | http://hdl.handle.net/10203/236496 | - |
dc.description.abstract | Disclosed herein is a divide-add circuit and a high-resolution Digital-to-Analog Converter (DAC) using the same. The DAC includes a plurality of DAC units and one or more divide-add circuit units. The plurality of DAC units performs Digital-Analog (DA) conversion on two or more segmented codes, into which an input digital code is segmented. The one or more divide-add circuit units is configured to be each composed only of capacitors and switches and to generate a final DA conversion output for the entire input digital code based on the voltages of the DAC units. Accordingly, a high resolution of more than ten bits can be implemented. | - |
dc.title | Divide-add circuit and high-resolution digital-to-analog converter using the same | - |
dc.type | Patent | - |
dc.type.rims | PAT | - |
dc.contributor.localauthor | 조규형 | - |
dc.contributor.assignee | KAIST | - |
dc.identifier.iprsType | 특허 | - |
dc.identifier.patentApplicationNumber | 11398868 | - |
dc.identifier.patentRegistrationNumber | 7283077 | - |
dc.date.application | 2006-04-06 | - |
dc.date.registration | 2007-10-16 | - |
dc.publisher.country | US | - |
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