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Showing results 1 to 7 of 7

1
A New Approach to the Multiport Memory Allocation Problem in Data Path Synthesis

Taewhan Kim; C.L. Liu, INTEGRATION-THE VLSI JOURNAL, v.19, no.3, pp.133 - 160, 1995-10

2
A stepwise refinement synthesis of digital systems for testability enhancement

Kim, Taewhan; Chung, KS; Liu, CL, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E82A, no.6, pp.1070 - 1081, 1999-06

3
Bus optimization for low power in high-level synthesis

Hong, S; Kim, Taewhan, JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, v.12, pp.1 - 17, 2003-02

4
Circuit Optimization using Carry-Save-Adder Cells

Taewhan Kim; William Jao; Steve Tjiang, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.17, no.10, pp.974 - 984, 1998-10

5
Coupling-aware high-level interconnect synthesis

Lyuh, CG; Kim, Taewhan; Kim, KW, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.23, no.1, pp.157 - 164, 2004-01

6
High-level Synthesis for Low-Power Based on Network Flow Method

chun-gi lyuh; taewhan kim, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.11, no.3, pp.364 - 375, 2003-06

7
Memory allocation and mapping in high-level synthesis - An integrated approach

Seo, J; Kim, Taewhan; Panda, PR, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.11, no.5, pp.928 - 938, 2003-10

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