Browse "RIMS Collection" by Author Chaeryung Park
Showing results 1 to 2 of 2
| An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization Chaeryung Park; Taewhan Kim; C.L. Liu, VLSI DESIGN, v.11, no.4, pp.381 - 396, 2000 |
| Register allocation - A hierarchical reduction approach Chaeryung Park; Kim, Taewhan; C.L. Liu, JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, v.19, no.3, pp.269 - 285, 1998 |
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