Showing results 25 to 41 of 41
Behavioral-Level Partitioning for Low Power Design in Control-Dominated Applications Taewhan Kim, ACM Great Lakes Symposium on VLSI (GLSVLSI), pp.156 - 161, 2000 |
Circuit Optimization using Carry-Save-Adder Cells Taewhan Kim; William Jao; Steve Tjiang, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.17, no.10, pp.974 - 984, 1998-10 |
Comments on the Originality of the Paper, ``The Integrated Scheduling and Allocation of High-Level Test synthesis'' Taewhan Kim, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS, v.E82-A, no.12, pp.2833 - 2833, 1999-12 |
Coupling-Aware Minimum Delay Optimization for Domino Logic Circuits Ki-Wook Kim; Seong-Ook Jung; Taewhan Kim; Sung-Mo Kang, ELECTRONICS LETTERS, v.37, no.13, pp.813 - 814, 2001-06 |
Domino Logic Synthesis based on Implication Graph for Set of Mandatory Assignments Ki-Wook Kim; Taewhan Kim; C.L. Liu; Sung-Mo Kang, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.21, no.2, pp.232 - 240, 2002-02 |
Enhanced Bus Invert Encoding for Low-Power Taewhan Kim, IEEE International SYmposium on Circuits and Systems, 2002 |
G-Vector: A New Model for Glitch Analysis Taewhan Kim, IEEE International ASIC/SOC Conference (ASIC), pp.159 - 162, 1999 |
Low Power Bus Encoding with Crosstalk Delay Elimination Taewhan Kim, IEEE ASIC/SOC Conference (ASIC), IEEE, 2002-09 |
Memory Exploration utilizing Scheduling Effects in High-level Synthesis Taewhan Kim, IEEE International Symposium on Circuits and Systems, IEEE, 2002-05 |
Memory Layout Technique for Variables Utilizing Efficient DRAM Access Modes in Embedded System Design Taewhan Kim, IEEE/ACM Design Automation Conference (DAC), pp.881 - 886, 2003 |
Optimal Voltage Allocation Techniques for Dynamically Variable Voltage Processors Taewhan Kim, IEEE/ACM Design Automation Conference (DAC), pp.125 - 130, 2003 |
Phase Assignment for the Synthesis of Low Power Domino Circuits Priyadasan Patra; Unni Narayanan; Taewhan Kim, ELECTRONICS LETTERS, v.37, no.13, pp.814 - 816, 2001-06 |
Power Optimization in VLSI Design based on Efficient Network Flow Computations Taewhan Kim, 6th Korea-Japan Workshop on ALgorithms and Computation, pp.3 - 8, 2001 |
Register Allocation for Dataflow Graphs with Conditional Branches and Loops Taewhan Kim, IEEE European Design Automation Conference (Euro-DAC), pp.232 - 237, 1993 |
Utilization of Carry-Save Adders in Arithmetic Optimization Taewhan Kim, IEEE International ASIC/SOC Conference (ASIC), pp.173 - 177, 1999 |
Utilization of Multiport Memories in Data Path Synthesis Taewhan Kim, ACM/IEEE Design Automation Conference (DAC), pp.298 - 302, 1993 |
Wallace-Tree based Timing-Driven Synthesis of Arithmetic Circuits Taewhan Kim, IEEE International Conference on VLSI and CAD (VLSICAD), pp.89 - 94, 1999 |
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