ANALOG-TO-DIGITAL CONVERTER고속 데이터 변환기를 위한 저전력 인터폴레이션 기법

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An analog-to-digital converter includes: a first latch row corresponding to a first stage; a second latch row corresponding to a second stage; and a digital processor for encoding output signals of the second latch row and generating a digital signal. The first latch row includes a plurality of first latches that receive an analog input signal and reference voltages and operate in synchronization with a first clock signal, and the second latch row includes: a plurality of second latches that receive outputs signals of the plurality of first latches and operate in synchronization with a second clock signal delayed from the first reference clock; and a plurality of third latches that receive output signals of two neighboring latches of the plurality of first latches and operate in synchronization with the second clock signal by means of an interpolation technique.
Assignee
KAIST
Country
US (United States)
Issue Date
2013-04-16
Application Date
2010-12-30
Application Number
12981664
Registration Date
2013-04-16
Registration Number
8,421,664
URI
http://hdl.handle.net/10203/234059
Appears in Collection
EE-Patent(특허)
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