DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ha, Jeong-Seok | ko |
dc.contributor.author | Cho, Sung-Gun | ko |
dc.date.accessioned | 2017-12-20T09:11:12Z | - |
dc.date.available | 2017-12-20T09:11:12Z | - |
dc.date.issued | 2015-10-20 | - |
dc.identifier.uri | http://hdl.handle.net/10203/232158 | - |
dc.description.abstract | The present disclosure relates to a BCH encoding, decoding, and multi-stage decoding circuits and method, and an error correction circuit of a flash memory device using the same. The concatenated BCH multi-stage decoding circuit includes: a first stage encoding unit that receives a part or all of data input to a flash memory device, performs BCH encoding, and outputs a first output BCH code or a parity bit thereof; an interleaving unit that receives a part or all of data input to the flash memory device, interleaves, and outputs the data, and a second stage encoding unit that performs BCH encoding of the BCH code or data that is the output of the interleaving unit, and outputs a second output BCH code or a parity bit thereof. | - |
dc.title | ENCODING, DECODING, AND MULTI-STAGE DECODING CIRCUITS FOR CONCATENATED BCH, AND ERROR CORRECTION CIRCUIT OF FLASH MEMORY DEVICE USING THE SAME | - |
dc.title.alternative | 연접 비씨에이치 부호, 복호 및 다계층 복호 회로 및 방법, 이를 이용한 플래쉬 메모리 장치의 오류 정정 회로 및 플래쉬 메모리 장치 | - |
dc.type | Patent | - |
dc.type.rims | PAT | - |
dc.contributor.localauthor | Ha, Jeong-Seok | - |
dc.contributor.nonIdAuthor | Cho, Sung-Gun | - |
dc.contributor.assignee | KAIST | - |
dc.identifier.iprsType | 특허 | - |
dc.identifier.patentApplicationNumber | 13678812 | - |
dc.identifier.patentRegistrationNumber | 9166626 | - |
dc.date.application | 2012-11-16 | - |
dc.date.registration | 2015-10-20 | - |
dc.publisher.country | US | - |
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