ENCODING, DECODING, AND MULTI-STAGE DECODING CIRCUITS FOR CONCATENATED BCH, AND ERROR CORRECTION CIRCUIT OF FLASH MEMORY DEVICE USING THE SAME 연접 비씨에이치 부호, 복호 및 다계층 복호 회로 및 방법, 이를 이용한 플래쉬 메모리 장치의 오류 정정 회로 및 플래쉬 메모리 장치

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 105
  • Download : 0
The present disclosure relates to a BCH encoding, decoding, and multi-stage decoding circuits and method, and an error correction circuit of a flash memory device using the same. The concatenated BCH multi-stage decoding circuit includes: a first stage encoding unit that receives a part or all of data input to a flash memory device, performs BCH encoding, and outputs a first output BCH code or a parity bit thereof; an interleaving unit that receives a part or all of data input to the flash memory device, interleaves, and outputs the data, and a second stage encoding unit that performs BCH encoding of the BCH code or data that is the output of the interleaving unit, and outputs a second output BCH code or a parity bit thereof.
Assignee
KAIST
Country
US (United States)
Issue Date
2015-10-20
Application Date
2012-11-16
Application Number
13678812
Registration Date
2015-10-20
Registration Number
9166626
URI
http://hdl.handle.net/10203/232158
Appears in Collection
EE-Patent(특허)
Files in This Item
There are no files associated with this item.

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0