SEMICONDUCTOR DEVICE HAVING JUNCTIONLESS VERTICAL GATE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME무접합 수직 게이트 트랜지스터를 갖는 반도체 소자 및 그 제조방법

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 173
  • Download : 0
A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.
Assignee
KAIST
Country
US (United States)
Issue Date
2015-09-15
Application Date
2013-02-05
Application Number
13759395
Registration Date
2015-09-15
Registration Number
9136376
URI
http://hdl.handle.net/10203/231488
Appears in Collection
EE-Patent(특허)
Files in This Item
There are no files associated with this item.

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0