A Supply Noise Insensitive PLL with a Rail-to-Rail Swing Ring Oscillator and a Wideband Noise Suppression Loop

Abstract

This paper presents a supply noise insensitive digital phaselocked loop (PLL) using a wide bandwidth noise suppression loop (NSL). Unlike previous techniques using regulation or calibration on the voltage-controlled oscillator (VCO) that lead to voltage headroom reduction, the proposed approach employs a wide bandwidth feedback loop around the oscillator, which suppresses supply noise without any headroom loss. The proposed dual loop PLL is implemented in 65nm CMOS, achieving spur suppression of about 30dB near PLL loop bandwidth, while consuming 2.73mW at 3.2GHz output.