DC Field | Value | Language |
---|---|---|
dc.contributor.author | Piersanti, Stefano | ko |
dc.contributor.author | de Paulis, Francesco | ko |
dc.contributor.author | Olivieri, Carlo | ko |
dc.contributor.author | Jung, Daniel Hyunsuk | ko |
dc.contributor.author | Kim, Joungho | ko |
dc.contributor.author | Orlandi, Antonio | ko |
dc.date.accessioned | 2017-09-25T05:10:45Z | - |
dc.date.available | 2017-09-25T05:10:45Z | - |
dc.date.created | 2017-09-11 | - |
dc.date.created | 2017-09-11 | - |
dc.date.issued | 2017-10 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, v.59, no.5, pp.1558 - 1564 | - |
dc.identifier.issn | 0018-9375 | - |
dc.identifier.uri | http://hdl.handle.net/10203/225970 | - |
dc.description.abstract | Small form factors and high bandwidth are two imperatives nowadays for three-dimensional integrated circuits (3-D-ICs). These requirements can be achieved by the use of through silicon vias, by the reduction of their radius and, at the same time, of the pitch among them. Having a considerable number of devices in a limited space inevitably increases the probability of the creation of defects (short, open, void, etc.). The study of the nature, topology, and creation mechanism of defects is crucial for 3-D-IC design. This paper suggests a procedure able to determine the nature of a defect (open-or short-circuit) and to estimate its position, basing its approach on the study of the electrical parameters of the defected structure, avoiding the use of invasive method such as Lock-in Thermography. A daisy-chain structure is manufactured and open or short defects are intentionally placed along the channel. With and without defects, the equivalent capacitance and inductance are extracted from the S-Parameters, from measurement and three-dimensional electromagnetic simulations, and used to define and validate the proposed procedure. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | COMPUTATIONAL ELECTROMAGNETICS CEM | - |
dc.subject | SELECTIVE VALIDATION FSV | - |
dc.title | Localization of Short and Open Defects in Multilayer Through Silicon Vias (TSV) Daisy-Chain Structures | - |
dc.type | Article | - |
dc.identifier.wosid | 000408330600022 | - |
dc.identifier.scopusid | 2-s2.0-85017418162 | - |
dc.type.rims | ART | - |
dc.citation.volume | 59 | - |
dc.citation.issue | 5 | - |
dc.citation.beginningpage | 1558 | - |
dc.citation.endingpage | 1564 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY | - |
dc.identifier.doi | 10.1109/TEMC.2017.2685348 | - |
dc.contributor.localauthor | Kim, Joungho | - |
dc.contributor.nonIdAuthor | Piersanti, Stefano | - |
dc.contributor.nonIdAuthor | de Paulis, Francesco | - |
dc.contributor.nonIdAuthor | Olivieri, Carlo | - |
dc.contributor.nonIdAuthor | Orlandi, Antonio | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Equivalent circuit model | - |
dc.subject.keywordAuthor | failure analysis | - |
dc.subject.keywordAuthor | open defect | - |
dc.subject.keywordAuthor | short defect | - |
dc.subject.keywordAuthor | through silicon via (TSV) | - |
dc.subject.keywordPlus | COMPUTATIONAL ELECTROMAGNETICS CEM | - |
dc.subject.keywordPlus | SELECTIVE VALIDATION FSV | - |
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