DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Minseo | ko |
dc.contributor.author | Ha, Unsoo | ko |
dc.contributor.author | Lee, Kyuho Jason | ko |
dc.contributor.author | Lee, Yongsu | ko |
dc.contributor.author | Yoo, Hoi-Jun | ko |
dc.date.accessioned | 2017-08-08T06:05:24Z | - |
dc.date.available | 2017-08-08T06:05:24Z | - |
dc.date.created | 2017-07-17 | - |
dc.date.created | 2017-07-17 | - |
dc.date.issued | 2017-07 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.52, no.7, pp.1953 - 1965 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/225081 | - |
dc.description.abstract | An ultra-low power true random number generator (TRNG) based on a sub-ranging SAR analog-to-digital converter (ADC) is proposed. The proposed TRNG is composed of a coarse-SAR ADC with a low-power adaptive-reset comparator and a low-power dynamic amplifier. The coarse-ADC part is shared with a sub-ranging SAR ADC for area reduction. The shared coarse-ADC not only plays the role of discrete-time chaotic circuit but also reduces the overall SAR ADC energy consumption by selectively activating the fine-SAR ADC. Also, the proposed dynamic residue amplifier consumes only 48 nW and the adaptive-reset comparator generates a chaotic map with only 6-nW consumption. The proposed TRNG core occupies 0.0045 mm(2) in 0.18-mu m CMOS technology and consumes 82 nW at 270-kbps throughput with 0.6-V supply. It successfully passes all of National Institute of Standards and Technology (NIST) tests, and it achieves the state-of-the-art figure-of-merit of 0.3 pJ/bit. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | CMOS | - |
dc.subject | ENTROPY | - |
dc.subject | IMPLEMENTATION | - |
dc.subject | SYSTEMS | - |
dc.subject | DESIGN | - |
dc.title | A 82-nW Chaotic Map True Random Number Generator Based on a Sub-Ranging SAR ADC | - |
dc.type | Article | - |
dc.identifier.wosid | 000404301300020 | - |
dc.identifier.scopusid | 2-s2.0-85018914009 | - |
dc.type.rims | ART | - |
dc.citation.volume | 52 | - |
dc.citation.issue | 7 | - |
dc.citation.beginningpage | 1953 | - |
dc.citation.endingpage | 1965 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2017.2694833 | - |
dc.contributor.localauthor | Yoo, Hoi-Jun | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article; Proceedings Paper | - |
dc.subject.keywordAuthor | Adaptive-reset comparator | - |
dc.subject.keywordAuthor | analog to digital conversion | - |
dc.subject.keywordAuthor | chaotic map | - |
dc.subject.keywordAuthor | cryptography | - |
dc.subject.keywordAuthor | encryption | - |
dc.subject.keywordAuthor | radio-frequency identification (RFID) | - |
dc.subject.keywordAuthor | security | - |
dc.subject.keywordAuthor | true random number generators (TRNGs) | - |
dc.subject.keywordPlus | CMOS | - |
dc.subject.keywordPlus | ENTROPY | - |
dc.subject.keywordPlus | IMPLEMENTATION | - |
dc.subject.keywordPlus | SYSTEMS | - |
dc.subject.keywordPlus | DESIGN | - |
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