Low-power and area-efficient FIR filter implementation suitable for multiple taps

Abstract

This paper describes a 32-tap finite impulse response (FIR) filter with two 16-tap macros suitable for multiple taps. The derived condition for a coded coefficient and data block shows 35% savings in power consumption and 44% improvement in occupied area compared to a typical radix-4 modified Booth algorithm. According to the condition and separated shifting-accessing clock scheme, we have implemented a 32-tap FIR filter in 0.6-mum CMOS technology with three levels of metal. The chip that occupies 2.3 X 2.5 mm(2) of silicon area has an operating frequency of 20 MHz and consumes 75 mW at V-dd = 3.3 V.