DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Yongjo | ko |
dc.contributor.author | Song, Keunsoo | ko |
dc.contributor.author | Kim, Dongkyun | ko |
dc.contributor.author | Cho, SeongHwan | ko |
dc.date.accessioned | 2017-06-05T02:21:01Z | - |
dc.date.available | 2017-06-05T02:21:01Z | - |
dc.date.created | 2016-11-18 | - |
dc.date.created | 2016-11-18 | - |
dc.date.created | 2016-11-18 | - |
dc.date.issued | 2017-04 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.64, no.4, pp.397 - 401 | - |
dc.identifier.issn | 1549-7747 | - |
dc.identifier.uri | http://hdl.handle.net/10203/223921 | - |
dc.description.abstract | In this brief, we propose a quadrature signal corrector for a low-power DDR4 mobile DRAM interface. In order to eliminate the phase imbalance among quadrature signals, the proposed architecture employs digitally controlled delay lines in a shared digital feedback loop with a time-multiplexed loop filter so as to minimize the effect of circuit mismatch that hampers the phase accuracy. A self-calibrated offset delay is also proposed, which allows the use of a simple 1-bit TDC instead of a power-hungry wide-dynamic range TDC. Implemented in 65-nm CMOS, the prototype chip achieves less than 1.1-ps phase error for a 1.25-GHz quadrature signal and occupies an active area of only 0.01 mm(2) while consuming 2.27 mW from a 1.0-V supply. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A 2.3-mW 0.01-mm(2) 1.25-GHz Quadrature Signal Corrector With 1.1-ps Error for Mobile DRAM Interface in 65-nm CMOS | - |
dc.type | Article | - |
dc.identifier.wosid | 000400566100009 | - |
dc.identifier.scopusid | 2-s2.0-85017608269 | - |
dc.type.rims | ART | - |
dc.citation.volume | 64 | - |
dc.citation.issue | 4 | - |
dc.citation.beginningpage | 397 | - |
dc.citation.endingpage | 401 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.identifier.doi | 10.1109/TCSII.2016.2569441 | - |
dc.contributor.localauthor | Cho, SeongHwan | - |
dc.contributor.nonIdAuthor | Song, Keunsoo | - |
dc.contributor.nonIdAuthor | Kim, Dongkyun | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Bang-bang phase detector (BBPD) | - |
dc.subject.keywordAuthor | digitally controlled delay line (DCDL) | - |
dc.subject.keywordAuthor | quadrature clock signal corrector | - |
dc.subject.keywordAuthor | time-multiplexed loop filter | - |
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