An Input Data and Power Noise Inducing Clock Jitter Tolerant Reference-Less Digital CDR for LCD Intra-Panel Interface

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This paper presents a reference-less digital clock and data recovery (CDR) for liquid crystal display (LCD) intrapanel interfaces. The increments of the display resolution, the color depth, and frame rate demand high speed transmission capacity between timing controller and source driver IC (SDIC). As the data rate increases, the performances of the CDR in the SDIC especially for the tolerance of input jitter and ground noise become important to recover the data without an error. This work exploits the half-bit previous input data with feed forward method and early/late signal from CDR to be tolerant to the input jitter and power noise. Two prototypes are tested with half-rate clocking at 5 Gb/s data rate, and quarter-late clocking at 10 Gb/s data rate. Both 5 Gb/s and 10 Gb/s prototypes improve the tolerance of the input jitter and power noise. Fabricated in 65 nm CMOS technology, the test chips consume 17.44 mW and 20.7 mW, respectively.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2017-04
Language
English
Article Type
Article
Keywords

DATA RECOVERY CIRCUIT; PHASE-LOCKED LOOP; SOI CMOS

Citation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.64, no.4, pp.823 - 835

ISSN
1549-8328
DOI
10.1109/TCSI.2016.2630119
URI
http://hdl.handle.net/10203/223703
Appears in Collection
EE-Journal Papers(저널논문)
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