Compressed On-Chip Framebuffer Cache for Low-Power Display Systems

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A framebuffer memory is data storage for the displayed image, which is one of the major power consumers in display systems. This paper proposes a power reduction technique for the on-chip framebuffer cache (FBC) performing a compressed image data management. The proposed architecture stores the compressed image data in the on-chip FBC, and the display controller decompresses the image data on the fly and sends it to the liquid crystal display panel. The compression and decompression processes incur additional power consumption but achieve lower system-wide power consumption. We implement the proposed architecture in a field-programmable gate array platform to confirm power saving by actual measurement. Experiments demonstrate that the proposed on-chip FBC significantly reduces the number of the off-chip framebuffer memory accesses and saves a large portion of the system-wide power consumption accordingly.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2017-04
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.25, no.4, pp.1215 - 1223

ISSN
1063-8210
DOI
10.1109/TVLSI.2016.2636849
URI
http://hdl.handle.net/10203/223669
Appears in Collection
EE-Journal Papers(저널논문)
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