Vertically Integrated Nanowire-Based Zero-Capacitor Dynamic Random Access Memory

Abstract

This paper demonstrates a breakthrough for DRAM scaling: A vertically integrated gate-all-around (GAA) silicon nanowire (SiNW) channel-based dynamic random access memory (DRAM) without a cell capacitor for data storage, i.e., a zero-capacitor DRAM unlike the conventional DRAM. Vertical integration of the SiNW was attained by a one-route all-dry etching process (ORADEP), resulting in stiction-free stability and simplicity in the fabrication process. High performance that is suitable for high packing density integration is presented with vertically integrated multiple channels, which reveals a potential for an ultimate scaling of DRAM toward the end of the roadmap. (C) The Author(s) 2016.