DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yoon, Taehun | ko |
dc.contributor.author | Lee, Joon Yeong | ko |
dc.contributor.author | Lee, Jinhee | ko |
dc.contributor.author | Han, Kwangseok | ko |
dc.contributor.author | Lee, Jeong-Sup | ko |
dc.contributor.author | Lee, Sangeun | ko |
dc.contributor.author | Kim, Taeho | ko |
dc.contributor.author | Han, Jinho | ko |
dc.contributor.author | Won, Hyo Sup | ko |
dc.contributor.author | Park, Jinho | ko |
dc.contributor.author | Bae, Hyeon-Min | ko |
dc.date.accessioned | 2017-04-17T07:27:02Z | - |
dc.date.available | 2017-04-17T07:27:02Z | - |
dc.date.created | 2017-04-10 | - |
dc.date.created | 2017-04-10 | - |
dc.date.created | 2017-04-10 | - |
dc.date.issued | 2017-03 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.52, no.3, pp.688 - 703 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/223241 | - |
dc.description.abstract | This paper presents the first 103.125-Gb/s multilink gearbox (MLG) IC, which facilitates the transport of independent 10-and 40-GbE signals to 4 x 25.78 Gb/s physical layers, such as 100GBASE-xR4. The IC consumes only 1.37 W while implementing complicated reverse gearbox functionality. The measured TX jitter from 10- and 25-G lanes is 0.407 and 0.448 psrms, respectively. The measured input sensitivities for a BER of 10(-1)2 of the 10- and 25-G RXs are 20 and 42 mVppd, respectively. The proposed gearbox IC, fabricated in a 40-nm CMOS process, occupies 3.7x3.4 mm(2). The power consumption of RX and TX in a 25-G interface is 50.9 and 52 mW, respectively, and those of a 10-G interface are 29 and 24.4 mW, respectively. MLG functionality is verified using embedded self-test logics. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | PHASE-LOCKED LOOP | - |
dc.subject | 40 NM CMOS | - |
dc.subject | TRANSCEIVER | - |
dc.subject | CLOCK | - |
dc.title | A 103.125-Gb/s Reverse Gearbox IC in 40-nm CMOS for Supporting Legacy 10-and 40-GbE Links | - |
dc.type | Article | - |
dc.identifier.wosid | 000396113900007 | - |
dc.identifier.scopusid | 2-s2.0-85009841197 | - |
dc.type.rims | ART | - |
dc.citation.volume | 52 | - |
dc.citation.issue | 3 | - |
dc.citation.beginningpage | 688 | - |
dc.citation.endingpage | 703 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2016.2636858 | - |
dc.contributor.localauthor | Bae, Hyeon-Min | - |
dc.contributor.nonIdAuthor | Lee, Jinhee | - |
dc.contributor.nonIdAuthor | Lee, Jeong-Sup | - |
dc.contributor.nonIdAuthor | Lee, Sangeun | - |
dc.contributor.nonIdAuthor | Kim, Taeho | - |
dc.contributor.nonIdAuthor | Han, Jinho | - |
dc.contributor.nonIdAuthor | Park, Jinho | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | 10 GbE | - |
dc.subject.keywordAuthor | 40 GbE | - |
dc.subject.keywordAuthor | 100 GbE | - |
dc.subject.keywordAuthor | CDR | - |
dc.subject.keywordAuthor | delay- and phase-locked loop (D/PLL) | - |
dc.subject.keywordAuthor | low power | - |
dc.subject.keywordAuthor | MLG 2.0 | - |
dc.subject.keywordAuthor | multilink gearbox (MLG) | - |
dc.subject.keywordAuthor | reference less | - |
dc.subject.keywordAuthor | reverse gearbox IC | - |
dc.subject.keywordAuthor | transceiver | - |
dc.subject.keywordPlus | PHASE-LOCKED LOOP | - |
dc.subject.keywordPlus | 40 NM CMOS | - |
dc.subject.keywordPlus | TRANSCEIVER | - |
dc.subject.keywordPlus | CLOCK | - |
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