DC Field | Value | Language |
---|---|---|
dc.contributor.author | Hong, Seul Ki | ko |
dc.contributor.author | Bong, Jae Hoon | ko |
dc.contributor.author | Cho, Byung-Jin | ko |
dc.contributor.author | Hwang, Wan Sik | ko |
dc.date.accessioned | 2017-04-14T08:16:03Z | - |
dc.date.available | 2017-04-14T08:16:03Z | - |
dc.date.created | 2016-11-18 | - |
dc.date.created | 2016-11-18 | - |
dc.date.created | 2016-11-18 | - |
dc.date.issued | 2017-01 | - |
dc.identifier.citation | SMALL, v.13, no.3 | - |
dc.identifier.issn | 1613-6810 | - |
dc.identifier.uri | http://hdl.handle.net/10203/223101 | - |
dc.description.abstract | A 100-nm wide, vertically formed graphene stripe (GS) is demonstrated for three-dimensional (3D) electronic applications. The GS forms along the sidewall of a thin nickel film. It is possible to further scale down the GS width by engineering the deposited thickness of the atomic layer deposition (ALD) Ni film. Unlike a conventional GS or graphene nanoribbon (GNR), the vertically formed GS is made without a graphene transfer and etching process. The process integration of the proposed GS FETs resembles that of currently commercialized vertical NAND flash memory with a design rule of less than 20 nm, implying practical usage of this formed GS for 3D advanced FET applications. | - |
dc.language | English | - |
dc.publisher | WILEY-V C H VERLAG GMBH | - |
dc.title | Vertically Formed Graphene Stripe for 3D Field-Effect Transistor Applications | - |
dc.type | Article | - |
dc.identifier.wosid | 000396567600006 | - |
dc.identifier.scopusid | 2-s2.0-85002188965 | - |
dc.type.rims | ART | - |
dc.citation.volume | 13 | - |
dc.citation.issue | 3 | - |
dc.citation.publicationname | SMALL | - |
dc.identifier.doi | 10.1002/smll.201602373 | - |
dc.contributor.localauthor | Cho, Byung-Jin | - |
dc.contributor.nonIdAuthor | Hwang, Wan Sik | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordPlus | EDGES | - |
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