Smart ECC Allocation Cache Utilizing Cache Data Space

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dc.contributor.authorHong, Jeongkyuko
dc.contributor.authorKim, Soontaeko
dc.date.accessioned2017-03-30T09:20:06Z-
dc.date.available2017-03-30T09:20:06Z-
dc.date.created2016-12-27-
dc.date.created2016-12-27-
dc.date.created2016-12-27-
dc.date.issued2017-02-
dc.identifier.citationIEEE TRANSACTIONS ON COMPUTERS, v.66, no.2, pp.368 - 374-
dc.identifier.issn0018-9340-
dc.identifier.urihttp://hdl.handle.net/10203/222744-
dc.description.abstractConventional error correcting codes (ECC) for caches are applied to all cache lines and stored in dedicated SRAM storage, which incurs both space and energy overheads. In contrast, we propose a Smart ECC Allocation (SEA) cache that utilizes cache data space for low-cost error protection of last-level caches. SEA cache avoids the requirement for dedicated storage for ECC check bits, which are stored in cache lines as data. To effectively utilize cache space, we group several cache sets and manage them according to program behavior. SEA cache eliminates the considerable space overheads of conventional ECC schemes without noticeable reliability and performance degradation.-
dc.languageEnglish-
dc.publisherIEEE COMPUTER SOC-
dc.subjectRELIABILITY-
dc.subjectIMPROVE-
dc.subjectCYCLE-
dc.titleSmart ECC Allocation Cache Utilizing Cache Data Space-
dc.typeArticle-
dc.identifier.wosid000394171000015-
dc.identifier.scopusid2-s2.0-85009986453-
dc.type.rimsART-
dc.citation.volume66-
dc.citation.issue2-
dc.citation.beginningpage368-
dc.citation.endingpage374-
dc.citation.publicationnameIEEE TRANSACTIONS ON COMPUTERS-
dc.identifier.doi10.1109/TC.2016.2595570-
dc.contributor.localauthorKim, Soontae-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorReliability-
dc.subject.keywordAuthorcache memory-
dc.subject.keywordAuthortransient error-
dc.subject.keywordAuthorerror-protection-
dc.subject.keywordPlusRELIABILITY-
dc.subject.keywordPlusIMPROVE-
dc.subject.keywordPlusCYCLE-
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