DC Field | Value | Language |
---|---|---|
dc.contributor.author | Nam, I | ko |
dc.contributor.author | Lee, Kwyro | ko |
dc.date.accessioned | 2011-02-18T09:25:16Z | - |
dc.date.available | 2011-02-18T09:25:16Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2005-02 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.40, pp.392 - 402 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/22239 | - |
dc.description.abstract | The electrical characteristics of the parasitic vertical NPN (V-NPN) BJT available in deep n-well 0.18-mum CMOS technology are presented. It has about, 20 of current gain, 7 V of collector-emitter breakdown voltage, 20 V of collector-base breakdown voltage, 40 V of Early voltage, about 2 GHz of cutoff frequency, and about 4 GHz of maximum oscillation frequency at room temperature. The corner frequency of 1/f noise is lower than 4 kHz at 0.5 mA of collector current. The double-balanced RF mixer using V-NPN shows almost free 1/f noise as well as an order of magnitude smaller dc offset compared with CMOS circuit and 12 dB flat gain almost up to the cutoff frequency. The V-NPN operational amplifier for baseband analog circuits has higher voltage gain and better input noise and input offset performance than the CMOS ones at the identical current. These circuits using V-NPN provide the possibility of high-performance direct conversion receiver implementation in CMOS technology. | - |
dc.description.sponsorship | The authors appreciate useful discussion with Dr. Y. J. Kim at Samsung Electronics and Dr. B. Kim at Integrant Technologies. The authors thank the reviewers for valuable comments and advice, and Dr. S. Hyun at ETRI and Dr. B. Kim at Integrant Technologies for their support. | en |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | RECEIVER | - |
dc.title | High-performance RF mixer and operational amplifier BiCMOS circuits using parasitic vertical bipolar transistor in CMOS technology | - |
dc.type | Article | - |
dc.identifier.wosid | 000226616900004 | - |
dc.identifier.scopusid | 2-s2.0-13444291510 | - |
dc.type.rims | ART | - |
dc.citation.volume | 40 | - |
dc.citation.beginningpage | 392 | - |
dc.citation.endingpage | 402 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Lee, Kwyro | - |
dc.contributor.nonIdAuthor | Nam, I | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | BiCMOS | - |
dc.subject.keywordAuthor | deep n-well CMOS | - |
dc.subject.keywordAuthor | direct conversion receiver | - |
dc.subject.keywordAuthor | offset | - |
dc.subject.keywordAuthor | operational amplifier | - |
dc.subject.keywordAuthor | parasitic vertical bipolar transistor | - |
dc.subject.keywordAuthor | RF mixer | - |
dc.subject.keywordAuthor | 1/f noise | - |
dc.subject.keywordPlus | RECEIVER | - |
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