Highly linear and efficient CMOS RF power amplifier for mobile applications

Abstract

For the highly linear and efficient CMOS RF power amplifier (PA) for mobile applications (WCDMA/LTE), two gate bias circuits and cross-coupled capacitors are applied in a differen-tial cascode structure PA with a dual-mode TLT. Since the gate bias determines the amplifier`s linearity, the integrated gate bias circuits are proposed in each amplifier, common-source (CS) and common-gate (CG) amplifier, to enhance the linearity in the cascode structure CMOS PA. In CS amplifier, the proposed Class-D bias circuit at the gate of a CS amplifier injects a re-shaped envelope signal only when the envelope signal is above a certain threshold voltage. This improves the linearity of the PA without significantly degrading the efficiency in a high-power region. In addition, the proposed bias circuit at the gate of a CG amplifier controls the second-order nonlinear components to reduce the sideband (IMD or ACLR) asymmetry and reduce sideband magnitude, simultaneously. For reducing the AM-PM distortion, cross-coupled capacitors are used in CS amplifiers of differential cascode structure. We find the relation between IMD3 magnitude and AM-PM distortion, analysis about the effect of cross-coupled capacitor on nonlinear gate capacitors in cascode structure, and improve the linearity of the PA in terms of error vector magnitude (EVM) and ACLR. Furthermore, a fully integrated dual-mode CMOS PA is proposed with a novel on-chip transformer to enhance the low power efficiency which enhances the battery life time. The transformer combines the output power from the differential amplifier in high-power mode and transmits the output power from the single-ended amplifier in low-power mode. The mode is changed by two shunt switches which help minimize the efficiency degradation and complete the output matching in each mode.