DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Shin, Youngsoo | - |
dc.contributor.advisor | 신영수 | - |
dc.contributor.author | Kim, Sangmin | - |
dc.contributor.author | 김상민 | - |
dc.date.accessioned | 2017-03-29T02:48:20Z | - |
dc.date.available | 2017-03-29T02:48:20Z | - |
dc.date.issued | 2016 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=648234&flag=dissertation | en_US |
dc.identifier.uri | http://hdl.handle.net/10203/222325 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2016.2 ,[viii, 78 p. :] | - |
dc.description.abstract | A dual-mode circuit is a circuit that has two operating modes: a default high-performance mode at nominal voltage and a secondary low-performance near-threshold voltage (NTV) mode. A key problem that is addressed is to minimize performance loss at NTV or maximize NTV mode clock frequency. A standard cell library for dual-mode circuits is proposed | - |
dc.description.abstract | transistor sizes are balanced and stack transistors are reduced. Gate sizing is performed to minimize negative slacks at both modes | - |
dc.description.abstract | a new sensitivity measure is introduced for this purpose | - |
dc.description.abstract | binary search is then applied to find the maximum NTV mode frequency. Clock tree synthesis is re-formulated to minimize clock skew at both modes. This is motivated by the fact that the proportion of load-dependent delay along clock paths, as well as clock path delays themselves, should be made equal. Experiments on test circuits indicate that NTV mode clock frequency is increased by 39% on average | - |
dc.description.abstract | clock skew at NTV decreases by 15% on average. Overall, NTV mode clock frequency is increased on average by 32%, while circuit area and energy consumption is increased by 4% and 5%, respectively. | - |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | clock tree optimization | - |
dc.subject | dual-mode circuit | - |
dc.subject | gate sizing | - |
dc.subject | near-threshold voltage | - |
dc.subject | timing optimization | - |
dc.subject | 게이트 사이징 | - |
dc.subject | 듀얼 모드 회로 | - |
dc.subject | 문턱전압 근처 전압 | - |
dc.subject | 클럭 트리 최적화 | - |
dc.subject | 타이밍 최적화 | - |
dc.title | Synthesis and optimization of dual operational-mode circuits | - |
dc.title.alternative | 듀얼 동작 모드 회로의 합성과 최적화 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 325007 | - |
dc.description.department | 한국과학기술원 :전기및전자공학부, | - |
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