DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Ryu, Seung-Tak | - |
dc.contributor.advisor | 류승탁 | - |
dc.contributor.author | Kwon, Ji-Wook | - |
dc.contributor.author | 권지욱 | - |
dc.date.accessioned | 2017-03-29T02:47:54Z | - |
dc.date.available | 2017-03-29T02:47:54Z | - |
dc.date.issued | 2016 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=663166&flag=dissertation | en_US |
dc.identifier.uri | http://hdl.handle.net/10203/222300 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2016.8 ,[iii, 43 p. :] | - |
dc.description.abstract | This dissertation proposes a low-power logarithmic resistance-to-digital converter (RDC) for multi-level cell (MLC) phase-change memory (PCM) readout. The proposed RDC is composed of a resistance-to-current converter (R2I) and a current-to-digital converter (I2D). A simple bleeding current source pair added to the R2I enhances the current settling speed and the sensing accuracy. The two-step I2D with a TDC-configured fine ADC could be designed with low-power consumption and small size owing to the time-reference generator that is shared by multiple channels and incorporates interpolation and size-scaling techniques. The total conversion time of the readout sensor including the R2I conversion is 100 ns, and the power consumption of a single-channel readout sensor is $60 \mu W$ under a 1.2 V supply. The ratio of the minimum decision step size to the full scale input current of the I2D corresponds to that of a conventional 9.6b linear ADC. The prototype chip is composed of 14-channels sharing a single time-reference generator, where each narrow single channel occupies $19 \mu m × 590 \mu m$ in a 65nm CMOS process. | - |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | resistance sensor | - |
dc.subject | resistance-to-digital converter (RDC) | - |
dc.subject | time-to-digital converter (TDC) | - |
dc.subject | phase-change memory (PCM) | - |
dc.subject | Logarithmic ADC | - |
dc.subject | 저항 센서 | - |
dc.subject | 저항-디지털 변환기 | - |
dc.subject | 시간-디지털 변환기 | - |
dc.subject | 상변화 메모리 | - |
dc.subject | 로그 아날로그-디지털 변환기 | - |
dc.title | Logarithmic resistance-to-digital converter for multi-level cell phase change memory readout | - |
dc.title.alternative | 멀티레벨 상변화 메모리의 readout을 위한 로그 저항-디지털 변환기 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 325007 | - |
dc.description.department | 한국과학기술원 :전기및전자공학부, | - |
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