DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Ryu, Seung-Tak | - |
dc.contributor.advisor | 류승탁 | - |
dc.contributor.author | Kim, Wan | - |
dc.contributor.author | 김완 | - |
dc.date.accessioned | 2017-03-29T02:47:52Z | - |
dc.date.available | 2017-03-29T02:47:52Z | - |
dc.date.issued | 2016 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=663168&flag=dissertation | en_US |
dc.identifier.uri | http://hdl.handle.net/10203/222298 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2016.8 ,[v, 62 p. :] | - |
dc.description.abstract | With growing demand for ultra-low-power applications, low-supply-voltage circuit design has been an attractive and plausible option for low-power system designs. However, high-performance analog/mixed-signal circuit designs become difficult under a low supply voltage because of the degraded operational speed, signal-to-noise ratio (SNR) degradation due to the reduced signal power, and the increased clock jitter. In order to overcome these limitations, an asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC is proposed as a suitable architecture in a low-supply-voltage condition. Settling-While-Conversion enabled by the Assist-ADC relaxes the DAC settling time requirement and makes it possible to insert a minimized capacitor shuffling logic with no speed penalty. A proposed gain-boosting dynamic pre-amplifier enhances the noise performance of the comparator and a self time-reference generation function is embedded in the pre-amplifier for a speed-enhanced asynchronous decision. A proposed dual-mode clock generator generates a low-jitter fixed-width sampling pulse for high frequency operation while it generates a low-power-but-low-quality clock for low frequency operation. With the dual-mode clock generator enabled, a prototype 65nm CMOS 0.6V 12b 10MS/s ADC achieves an ENOB of 10.4 at a Nyquist-rate input, and the peaks of DNL and INL are measured to be 0.24LSB and 0.45LSB, respectively. The FoM is 6.2fJ/conversion-step with a power consumption of $83 \mu W$ . The ADC operates under the lowest supply voltage of 0.6V among comparable designs with ENOBs over 10 and conversion rates over 1MS/s. | - |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | Low voltage | - |
dc.subject | Asynchronous SAR ADC | - |
dc.subject | SAR-Assisted Time-Interleaved SAR | - |
dc.subject | SATI-SAR | - |
dc.subject | Low-noise comparator | - |
dc.subject | Gain-boosting dynamic comparator | - |
dc.subject | Low-jitter clock | - |
dc.subject | 저 전압 | - |
dc.subject | 비동기식 SAR ADC | - |
dc.subject | 저 잡음 비교기 | - |
dc.subject | Low-jitter 클럭 | - |
dc.title | Low-noise time-interleaved SAR ADC for low-supply voltage applications | - |
dc.title.alternative | 저 전압 응용을 위한 저 잡음 시-병렬 축차 비교형 아날로그-디지털 변환기 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 325007 | - |
dc.description.department | 한국과학기술원 :전기및전자공학부, | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.