Subpage based flash translation layer for solid state drivers

Abstract

Solid State Drive (SSD) which consists of NAND flash chip is widely used to high performance computer system because of high speed. Current computer system uses sector unit (512B) to I/O operation. However, the minimum read and write unit is page which size is 4KB ~ 16KB in NAND flash chip. Thus, address translation is needed in SSD. Unlike conventional volatile memories, NAND flash chip cannot update same location which is called out-place update and has limited P/E cycle which is related to lifetime of SSD. Because of these characteristic, if subpage write which request size is less than page unit is coming, NAND flash chip has to read stored old data and modify and write to new location which is called Read Modify Write (RMW). As vendors increase page size to increase throughput of SSD, subpage write ratio is also increased. Moreover, current mapping table which has responsible for address translation dose not have stored information of physical page. Thus, conventional mapping table cannot detect unnecessary RMW which new write request can cover the stored old data. In this paper, we propose Subpage based Flash Translation Layer (FTL) to reduce the number of writes which can improve lifetime and increase performance. The subpage based FTL can merge subpage write requests in write buffer and added stored data information to mapping table to detect unnecessary RMW. We experimented subpage base FTL using trace based simulation. The result of reduction write operation is maximum 23% and 13% on average. Also, we can reduce write latency to maximum 13% and 9% on average.