Capacitance-to-digital converter based on power detection전력검출에 기반한 커패시턴스-디지털 변환회로

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dc.contributor.advisorYoo, Hyung-Joun-
dc.contributor.advisor유형준-
dc.contributor.authorVelazquez Lopez, Mauricio-
dc.date.accessioned2017-03-29T02:38:27Z-
dc.date.available2017-03-29T02:38:27Z-
dc.date.issued2016-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=649574&flag=dissertationen_US
dc.identifier.urihttp://hdl.handle.net/10203/221768-
dc.description학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2016.2 ,[vi, 57 p. :]-
dc.description.abstractCapacitance-to-digital converters (CDC) help transform a change in capacitance, usually coming from a capacitive sensor, into an exploitable digital word. The various performance characteristics expected from these type of circuits makes their design particularly challenging. Therefore, CDC designs are diverse and involve many different techniques each one with its own set of advantages and disadvantages. This thesis proposes a CDC based on power detection which consists in relating a variation in capacitance to a change in power by means of the attenuation of an input fundamental tone passing through a low-pass filter that contains the capacitive element to be interfaced. Recently, research has focused on widening the capacitive range and resolution of these circuits. High resolution CDCs usually have severe capacitance range limitations or high power consumption which limits their applications. This thesis describes a highly adaptable 16-bit CDC based on power detection with wide capacitance range (nearly 1 nF) whose power consumption, measuring time and circuit capacitors are fixed and independent from the actual capacitance measurements regardless of the sensor's capacitance size. This CDC counts with a variable capacitance resolution which can be adjusted depending on the requirements of each sensor. Additionally, its multistage power detector provides the CDC with three different sensitivity rates making it possible to interface one capacitive sensor with three different sensitivities or three different sensors with their own sensitivity requirements each. This high versatility relies on the different configurations of the system as well as on two main blocks: the multi-stage power detection block and the low-pass filter that includes the variable capacitive element. An on-chip low-pass filter was added to prove the method’s reliability for on-chip applications. The circuit was designed using a TSMC $0.25-\mu m$ CMOS technology, operates at a single 2.5-V supply, and consumes less than 1.86 mW.-
dc.languageeng-
dc.publisher한국과학기술원-
dc.subjectcapacitance-to-digital converter-
dc.subjectcapacitive sensor-
dc.subjectpower detection-
dc.subjectmulti stage detection-
dc.subjectwide sensing range-
dc.subject커패시턴스-디지털 변환회로-
dc.subject정전식 센서-
dc.subject전력 검출-
dc.subject다단식 검출-
dc.subject광범위 센싱-
dc.titleCapacitance-to-digital converter based on power detection-
dc.title.alternative전력검출에 기반한 커패시턴스-디지털 변환회로-
dc.typeThesis(Master)-
dc.identifier.CNRN325007-
dc.description.department한국과학기술원 :전기및전자공학부,-
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EE-Theses_Master(석사논문)
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