Hard-information based majority-logic decoding method and structure for non-binary LDPC codes

Abstract

Non-binary low-density parity-check (NB-LDPC) codes have been actively researched recently due to their superior error-correcting performances compared to those of binary counterparts when the code length is moderate. However, the performance comes at the expense of the high decoding complexity. Recently, reasonable complexity-performance trade-off algorithms have been developed called iterative reliability-based majority-logic decoding algorithms. In this paper, we focus on an iterative hard reliability-based majority-logic decoding (IHRB-MLgD) algorithm which uses only hard-information from the channel to consider the practical case that using soft-information is hard such as NAND flash-based storage systems. This paper proposes two improved IHRB-MLgD algorithms. One is an algorithm which improves an error performance with simply modified initialization. The other is a hardware-friendly algorithm which reduces the memory size considerably while keeping the error performance obtained by simply modified initialization. The memory size is reduced about 72% compared to that of conventional one. Based on the hardware-friendly algorithm, a low-complexity partial-parallel NB-LDPC decoder architecture is developed and also implemented in 65nm CMOS technology. According to implementation results, the core area of the proposed algorithm also slightly reduced compared to that of the conventional algorithm.