Incremental sigma delta ADC for high resolution low power sensor

Abstract

This paper introduces Incremental $\Sigma \Delta$ ADC for high resolution low power sensor. It is based on a power-efficient zoom ADC architecture, which consists of a coarse 4-bit SAR ADC and a fine incremental $\Sigma \Delta$ ADC. To reduce total conversion cycle, the zoom ADC utilizes $3^{rd}$ order noise shaping characteristic which is achieved by a study MASH architecture. Unlike conventional MASH structures, the sturdy MASH architecture alleviates the gain requirement of integrators due to the removal of digital cancelation logic. Utilizing zoom and study MASH architecture together, Incremental Zoom Sturdy MASH architecture is proposed. The requirement of amplifiers is significantly relaxed due to the proposed architecture and it allows the realization of a low power architecture. The zoom ADC with SAR and $\Sigma \Delta$ ADC is implemented in 0.35um CMOS process. Simulation result shows that $3^{rd}$ order noise shaping and 18bit resolution in conversion time of 606us is achieved, while consuming 161uA current from 3.3V supply.