(An) injection locked phase locked loop with low reference spur

Abstract

In various wireline communication systems, clock is essential for data sampling, analog to digital conversion, etc. Thus, integer-N PLL is widely used for clock generating because its good phase noise performance. However, PLL output noise performance is degraded by PLL’s each block noises which are divider, phase frequency detector and charge pump noise. Over the past few years, several studies have been conducted for implementation of low phase noise integer-N PLL. Sub-harmonically injection locked PLL (ILPLL) is a representative method for achieving low phase noise. In this paper, we proposed two type of ILPLL with low reference spur level. First work is using injection locked oscillator (ILO) divider in ILPLL. Delay line in injection path of conventional ILPLL is noise source. Thus it makes injected reference clock to noisy. If ILO divider is used, delay line can be removed in injection path. Therefore proposed work has a good phase noise performance. In addition, that has another advantage for injection timing calibration. It make calibration method to simple and low power consumption, thus calibration circuit can be operated in background. Thus system is robust to voltage and temperature variation Second work is divider-less ILPLL with simple phase detector. Previous divider-less ILPLL has a modified phase detector to compare different frequency clock. However this phase detector has problems which are mismatch between phase-frequency detectors and charge pumps, and control voltage ripple problem. We resolve these two problems using simple phase detector and control voltage ripple compensation method. It is made to obtain a better phase noise performance. Proposed 2GHz ILPLLs were implemented by 65nm CMOS process with 3.9-mW and 4.1-mW power consumption. The simulated reference spur levels are -57.2 dBc and -54.6 dBc.