DC Field | Value | Language |
---|---|---|
dc.contributor.author | Hanjoon Kim | - |
dc.contributor.author | Heo, Seulki | - |
dc.contributor.author | Lee , Junghoon | - |
dc.contributor.author | Huh, Jaehyuk | - |
dc.contributor.author | Kim, John Dongjun | - |
dc.date.accessioned | 2011-02-14T08:24:42Z | - |
dc.date.available | 2011-02-14T08:24:42Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2010-11-13 | - |
dc.identifier.citation | 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis, SC 2010, v.0, no.0, pp.0 - 0 | - |
dc.identifier.uri | http://hdl.handle.net/10203/22129 | - |
dc.description.abstract | With the number of cores on a chip continuing to increase, proper evaluation of on-chip network is critical for not only network performance but also overall system performance. In this paper, we show how a network-only simulation can be limited as it does not provide an accurate representation of system performance. We evaluate traditionally used openloop simulations and compare them to closed-loop simulations. Although they use different methodologies, measurements, and metrics, we identify how they can provide very similar results. However, we show how the results of closed-loop simulations do not correlate well with execution-driven simulations. We then add simple extensions to the closed-loop simulation to model the impact of the processor and the memory system and show how the correlation with execution-driven simulations can be improved. The proposed framework/methodology provides a fast simulation time while providing better insights into the impact of network parameters on overall system performance. | - |
dc.description.sponsorship | The authors would like to thank the anonymous reviewers, Brian Towles, and James Balfour for their comments. This work was supported in part by the IT R&D Program of MKE/KEIT [2010-KI002090, Development of Technology Base for Trustworthy Computing] and in part by Microsoft Research Asia (MSRA) New Faculty Fellowship. | en |
dc.language | ENG | - |
dc.language.iso | en_US | en |
dc.publisher | ACM | - |
dc.title | On-chip network evaluation framework | - |
dc.type | Conference | - |
dc.identifier.scopusid | 2-s2.0-78650844034 | - |
dc.type.rims | CONF | - |
dc.citation.volume | 0 | - |
dc.citation.issue | 0 | - |
dc.citation.beginningpage | 0 | - |
dc.citation.endingpage | 0 | - |
dc.citation.publicationname | 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis, SC 2010 | - |
dc.identifier.conferencecountry | United States | - |
dc.identifier.conferencecountry | United States | - |
dc.contributor.localauthor | Huh, Jaehyuk | - |
dc.contributor.localauthor | Kim, John Dongjun | - |
dc.contributor.nonIdAuthor | Hanjoon Kim | - |
dc.contributor.nonIdAuthor | Heo, Seulki | - |
dc.contributor.nonIdAuthor | Lee , Junghoon | - |
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