A 2.4GHz 1.5mW digital MDLL using pulse-width comparator and double injection technique in 28nm CMOS

Abstract

A multiplying delay-locked loop (MDLL) is an attractive architecture for a low-jitter clock generator, as it does not suffer much from jitter accumulation [1-4]. By periodically replacing the output edge of the oscillator by a clean edge of the reference, an MDLL has a large effective loop bandwidth for oscillator phase noise, which cannot be obtained in a PLL. With this advantage in mind, several MDLLs have been implemented recently [2], [3]. Unfortunately, these works are limited in their practical use as the frequency multiplication factor is only 4 [2] or 8 [3]. While the prior works show good jitter performance, it is primarily due to their wide effective loop bandwidth of nearly one hundred MHz that arises from using reference frequencies of 375 to 575MHz. It is much more challenging to achieve same level of jitter performance if the multiplication factor is increased and reference frequency is decreased. In this work, a low-power digital MDLL (DMDLL) with a multiplication factor of 32 is presented. To achieve low-jitter despite the large multiplication factor, a background-calibrated double-injection scheme is proposed which exploits both the rising and falling edge of the reference.