Register grouping for synthesis of clock gating logic
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Han, In-Hak | - |
| dc.contributor.author | Kim, Jongkyou | - |
| dc.contributor.author | Yi, Junhwan | - |
| dc.contributor.author | Shin, Youngsoo | - |
| dc.date.accessioned | 2017-01-03T07:15:35Z | - |
| dc.date.available | 2017-01-03T07:15:35Z | - |
| dc.date.created | 2016-11-21 | - |
| dc.date.issued | 2016-06-27 | - |
| dc.identifier.citation | IEEE International Conference on IC Design and Technology (ICICDT) | - |
| dc.identifier.uri | http://hdl.handle.net/10203/215542 | - |
| dc.language | English | - |
| dc.publisher | IEEE/ACM | - |
| dc.title | Register grouping for synthesis of clock gating logic | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.citation.publicationname | IEEE International Conference on IC Design and Technology (ICICDT) | - |
| dc.identifier.conferencecountry | VN | - |
| dc.identifier.conferencelocation | 베트남 호치민시 | - |
| dc.contributor.localauthor | Han, In-Hak | - |
| dc.contributor.localauthor | Shin, Youngsoo | - |
| dc.contributor.nonIdAuthor | Kim, Jongkyou | - |
| dc.contributor.nonIdAuthor | Yi, Junhwan | - |
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