Through silicon via (TSV) based 3DIC has allowed vertical integration of multiple dies for wide I/O configuration. With thousands of TSVs, data transfer rate can be reduced, while maintaining the highest bandwidth compared to the systems in conventional integrated chips and packages. The challenges lie on high yield fabrication process. The trend in dimension of TSV is continuously decreasing, which also causes bumps and redistribution layer (RDL) to be reduced for routing high number of OI/Os. In this paper, we present the equivalent circuit models and analyze the TSV channels for investigation of the effect of possible defects. The verified models are used for characterizing the defects in TSV channel, and we validate the failure analysis method with electrical characteristic analysis in frequency domain with S-parameter plots as well as time-domain waveforms with TDR.