Area efficient neuromorphic circuit based on stochastic computation

Abstract

Neuromorphic circuit can be simplified by applying stochastic computing, which uses a bit stream. A large number of stochastic number generators (SNGs) allows independent bit streams and hence secures accuracy, but outweighs the advantage of stochastic computing in circuit area. An area efficient SNG design method is proposed, in which a single linear feedback shift register (LFSR) is shared among a number of SNGs; independency of bit streams is made possible through shuffled wiring between LFSR and bit stream generators. Proposed design method is applied to a neuromorphic circuit that recognizes handwritten numbers; circuit area is reduced by 86% while prediction accuracy is sacrificed by 11% compared to a reference design in which LFSR is not shared.