A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs

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dc.contributor.authorKim, Hyeon-Juneko
dc.contributor.authorHwang, Sun-Ilko
dc.contributor.authorKwon, Ji-Wookko
dc.contributor.authorJin, Dong-Hwanko
dc.contributor.authorChoi, Byoung-Sooko
dc.contributor.authorLee, Sang-Gwonko
dc.contributor.authorPark, Jong-Hoko
dc.contributor.authorShin, Jang-Kyooko
dc.contributor.authorRyu, Seung-Takko
dc.date.accessioned2016-11-30T08:33:42Z-
dc.date.available2016-11-30T08:33:42Z-
dc.date.created2016-11-16-
dc.date.created2016-11-16-
dc.date.issued2016-10-
dc.identifier.citationIEEE JOURNAL OF SOLID-STATE CIRCUITS, v.51, no.10, pp.2262 - 2273-
dc.identifier.issn0018-9200-
dc.identifier.urihttp://hdl.handle.net/10203/214236-
dc.description.abstractThis paper presents a power-saving readout scheme for CMOS image sensors (CISs) that utilizes the image properties. The proposed delta-readout (Delta-readout) scheme reads the signal difference between two pixels located next to each other (Delta(pixel)) by utilizing the most significant bits (MSBs) information of the previous pixel. By effectively reducing the dynamic range of the signal, compensated by the Delta-window checking, the proposed Delta-readout scheme can reduce the effective number of decision cycles in a successive-approximation register (SAR) analog-to-digital converter (ADC) and reduce the power consumption while preserving the ADC performance. A prototype QQVGA CIS with ten 10-bit SAR ADCs in a multi-column-parallel (MCP) configuration was fabricated in a 0.18 mu m 1P4M CIS process with a 4.4 mu m pixel pitch, where each single ADC occupies an area of 70 mu m x 500 mu m. The measurement results of the implemented prototype CIS showed a maximum power-saving of 26% with a figure-of-merit (FoM) for ADC of 15 fJ/conversion-step-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectDIGITAL ERROR-CORRECTION-
dc.subject10-B-
dc.subjectARRAY-
dc.subjectDAC-
dc.titleA Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs-
dc.typeArticle-
dc.identifier.wosid000385240200010-
dc.identifier.scopusid2-s2.0-84979884740-
dc.type.rimsART-
dc.citation.volume51-
dc.citation.issue10-
dc.citation.beginningpage2262-
dc.citation.endingpage2273-
dc.citation.publicationnameIEEE JOURNAL OF SOLID-STATE CIRCUITS-
dc.identifier.doi10.1109/JSSC.2016.2581819-
dc.contributor.localauthorRyu, Seung-Tak-
dc.contributor.nonIdAuthorChoi, Byoung-Soo-
dc.contributor.nonIdAuthorLee, Sang-Gwon-
dc.contributor.nonIdAuthorPark, Jong-Ho-
dc.contributor.nonIdAuthorShin, Jang-Kyoo-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorCMOS image sensor (CIS)-
dc.subject.keywordAuthorimage-dependent power savings-
dc.subject.keywordAuthordelta-readout (Delta-readout) scheme-
dc.subject.keywordAuthormulti-column-parallel (MCP)-
dc.subject.keywordAuthorsuccessive-approximation register analog-to-digital converter (SAR ADC)-
dc.subject.keywordPlusDIGITAL ERROR-CORRECTION-
dc.subject.keywordPlus10-B-
dc.subject.keywordPlusARRAY-
dc.subject.keywordPlusDAC-
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