DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Byung-Hyun | ko |
dc.contributor.author | Ahn, Dae-Chul | ko |
dc.contributor.author | Kang, Min-Ho | ko |
dc.contributor.author | Jeon, Seung-Bae | ko |
dc.contributor.author | Choi, Yang-Kyu | ko |
dc.date.accessioned | 2016-11-09T05:29:53Z | - |
dc.date.available | 2016-11-09T05:29:53Z | - |
dc.date.created | 2016-10-19 | - |
dc.date.created | 2016-10-19 | - |
dc.date.issued | 2016-09 | - |
dc.identifier.citation | NANO LETTERS, v.16, no.9, pp.5909 - 5916 | - |
dc.identifier.issn | 1530-6984 | - |
dc.identifier.uri | http://hdl.handle.net/10203/213773 | - |
dc.description.abstract | A vertically integrated nanowire-based device for multifunctional Unified, memory that combine dynamic random access memory (DRAM) and flash memory,,in a single transistor is demonstrated for the first time. The:device Utilizes a gate-all-around (GAA) structure that completely surrounds the nano-wire; the structure is built on a-bulk silicon wafer. A vertically integrated unified memory (VIUM) device composed of five-story channels was fabricated via the one-route all-dry etching process (ORADEP) reliable reproducibility, stiction-free stability, and high-uniformity. In each DRAM and flash memory operation, the five-story VIUM showed a remarkably enhanced sensing current drivability compared with one-story unified-memory (UM) characteristics. In addition-to-each independent memory mode, the switching endurance of the VIUM was evaluated in the unified mode, which alternatively activates two memory modes, resulting in an even higher sensing Memory window-than that of the UM. In addition to our previous work on a logic transistor joining high performance with good scalability this work describes a novel memory hierarchy design with high functionality for system-on-chip (SoC) architectures, demonstrating the practicality and versatility of the vertically integrated nanowire configuration for use in various applications | - |
dc.language | English | - |
dc.publisher | AMER CHEMICAL SOC | - |
dc.title | Vertically Integrated Nanowire-Based Unified Memory | - |
dc.type | Article | - |
dc.identifier.wosid | 000383412100087 | - |
dc.identifier.scopusid | 2-s2.0-84987748089 | - |
dc.type.rims | ART | - |
dc.citation.volume | 16 | - |
dc.citation.issue | 9 | - |
dc.citation.beginningpage | 5909 | - |
dc.citation.endingpage | 5916 | - |
dc.citation.publicationname | NANO LETTERS | - |
dc.identifier.doi | 10.1021/acs.nanolett.6b02824 | - |
dc.contributor.localauthor | Choi, Yang-Kyu | - |
dc.contributor.nonIdAuthor | Ahn, Dae-Chul | - |
dc.contributor.nonIdAuthor | Kang, Min-Ho | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Vertically integrated nanowire | - |
dc.subject.keywordAuthor | zRAM | - |
dc.subject.keywordAuthor | 1T-DRAM | - |
dc.subject.keywordAuthor | NAND flash memory | - |
dc.subject.keywordAuthor | unified memory | - |
dc.subject.keywordAuthor | One-route all-dry etching process | - |
dc.subject.keywordPlus | RAM URAM | - |
dc.subject.keywordPlus | TRANSISTORS | - |
dc.subject.keywordPlus | TECHNOLOGY | - |
dc.subject.keywordPlus | FUTURE | - |
dc.subject.keywordPlus | DEVICE | - |
dc.subject.keywordPlus | CELL | - |
dc.subject.keywordPlus | 1T-DRAM | - |
dc.subject.keywordPlus | LIMITS | - |
dc.subject.keywordPlus | NVM | - |
dc.subject.keywordPlus | NM | - |
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