DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kwon, HJ | ko |
dc.contributor.author | Lee, Kwyro | ko |
dc.date.accessioned | 2011-01-04T06:13:07Z | - |
dc.date.available | 2011-01-04T06:13:07Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 1999-02 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, v.46, no.2, pp.202 - 209 | - |
dc.identifier.issn | 1057-7130 | - |
dc.identifier.uri | http://hdl.handle.net/10203/21353 | - |
dc.description.abstract | A nem polynomial division algorithm in finite field GF(2(m)) based on the lookahead of partial-remainder (LAPR) is proposed. Since our algorithm is based on partial division on group basis and lookahead technique exploiting the linearity in finite field arithmetic, it is possible to completely eliminate polynomial multiplications leading to highly increased throughput per unit time. The inherent regularity and feedforward nature of our algorithm make it possible to be fully pipelined, When pipelined, its throughput is one quotient and one remainder per clock cycle, regardless of the degree of dividend polynomial, which is orders of magnitude faster than the conventional architecture using linear feedback shift register. An area-efficient sequential architecture based on LAPR is also presented. Although the throughput rate of sequential architecture is lower than that of the pipelined one, it is still higher than that of any division architecture ever reported. Those will be shown to be efficient, regular, and easily expandable, and hence, naturally suitable for very large scale integration implementation. In systems requiring modest speed, the high-speed nature of our proposed architecture can be traded for low-power consumption by reducing clock rate. We verified the general validity of the division algorithm based on LAPR bg mathematical manipulation and simulation. The superiority of our proposed architecture compared with other reported ones is demonstrated,vith regard to its throughput, latency delays, and power. | - |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | REED-SOLOMON ENCODER | - |
dc.subject | DESIGN | - |
dc.title | A new division algorithm based on lookahead of partial-remainder (LAPR) for high-speed/low-power coding applications | - |
dc.type | Article | - |
dc.identifier.wosid | 000079296300016 | - |
dc.identifier.scopusid | 2-s2.0-0033075668 | - |
dc.type.rims | ART | - |
dc.citation.volume | 46 | - |
dc.citation.issue | 2 | - |
dc.citation.beginningpage | 202 | - |
dc.citation.endingpage | 209 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Lee, Kwyro | - |
dc.contributor.nonIdAuthor | Kwon, HJ | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordPlus | REED-SOLOMON ENCODER | - |
dc.subject.keywordPlus | DESIGN | - |
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