DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Youngjoo | ko |
dc.contributor.author | Jung, Jaehwan | ko |
dc.contributor.author | Park, In-Cheol | ko |
dc.date.accessioned | 2016-10-07T09:33:19Z | - |
dc.date.available | 2016-10-07T09:33:19Z | - |
dc.date.created | 2015-11-23 | - |
dc.date.created | 2015-11-23 | - |
dc.date.issued | 2016-02 | - |
dc.identifier.citation | IEICE TRANSACTIONS ON ELECTRONICS, v.E99C, no.2, pp.293 - 301 | - |
dc.identifier.issn | 1745-1353 | - |
dc.identifier.uri | http://hdl.handle.net/10203/213278 | - |
dc.description.abstract | This paper presents a novel low-power decoder architecture for the (36420, 32778) binary LDPC code targeting energy-efficient NAND-flash-based mobile devices. The proposed energy-scalable decoding algorithm reduces the operating bit-width of decoding function units at the early-use stage where the channel condition is good enough to lower the precision of computation. Based on a flexible adder structure, the decoding energy of the proposed LDPC decoder can be reduced by freezing the unnecessary parts of hardware resources. A prototype 4KB LDPC decoder is designed in a 65nm CMOS technology, which achieves an average decoding throughput of 8.13Gb/s with 1.2M equivalent gates. The power consumption of the decoder ranges from 397mW to 563mW depending on operating conditions. | - |
dc.language | English | - |
dc.publisher | IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG | - |
dc.subject | DECISION ERROR-CORRECTION | - |
dc.subject | RECOVERY SCHEMES | - |
dc.subject | MEMORY | - |
dc.subject | DESIGN | - |
dc.subject | PERFORMANCE | - |
dc.subject | CODES | - |
dc.title | Energy-Scalable 4KB LDPC Decoding Architecture for NAND-Flash-Based Storage Systems | - |
dc.type | Article | - |
dc.identifier.wosid | 000381557500019 | - |
dc.identifier.scopusid | 2-s2.0-84957649592 | - |
dc.type.rims | ART | - |
dc.citation.volume | E99C | - |
dc.citation.issue | 2 | - |
dc.citation.beginningpage | 293 | - |
dc.citation.endingpage | 301 | - |
dc.citation.publicationname | IEICE TRANSACTIONS ON ELECTRONICS | - |
dc.identifier.doi | 10.1587/transele.E99.C.293 | - |
dc.contributor.localauthor | Park, In-Cheol | - |
dc.contributor.nonIdAuthor | Lee, Youngjoo | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | energy-efficient design | - |
dc.subject.keywordAuthor | forward error-correction | - |
dc.subject.keywordAuthor | NAND flash memory | - |
dc.subject.keywordAuthor | VLSI designs | - |
dc.subject.keywordPlus | DECISION ERROR-CORRECTION | - |
dc.subject.keywordPlus | RECOVERY SCHEMES | - |
dc.subject.keywordPlus | MEMORY | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | PERFORMANCE | - |
dc.subject.keywordPlus | CODES | - |
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