DC Field | Value | Language |
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dc.contributor.author | Kim, Woo-Young | ko |
dc.contributor.author | Kim, Hyeon-Don | ko |
dc.contributor.author | Jeon, Gwang-Jae | ko |
dc.contributor.author | Kang, In-Ku | ko |
dc.contributor.author | Shim, Hyun Bin | ko |
dc.contributor.author | Kim, Tae-Hyo | ko |
dc.contributor.author | Lee, Hee Chul | ko |
dc.date.accessioned | 2016-09-07T04:23:38Z | - |
dc.date.available | 2016-09-07T04:23:38Z | - |
dc.date.created | 2016-08-29 | - |
dc.date.created | 2016-08-29 | - |
dc.date.issued | 2016-07 | - |
dc.identifier.citation | MICRO & NANO LETTERS, v.11, no.7, pp.356 - 359 | - |
dc.identifier.issn | 1750-0443 | - |
dc.identifier.uri | http://hdl.handle.net/10203/212876 | - |
dc.description.abstract | A ferroelectric-gated graphene field-effect transistor was fabricated by consecutively stacking two distinct graphene-ferroelectric hybrid ribbons at right angles. Two graphene layers play different roles. One graphene layer acts as a gate electrode and the other graphene layer acts as a channel between two electrodes, source and drain. Electric gating at the gate graphene modulates the resistance of the channel graphene. By means of ferroelectric polarisation, bistable resistance states of the channel graphene could be recorded, and the retention time of bistability was estimated to be 460 days by extrapolating of two resistance values in time-resistance relationships. Furthermore, the underlying concept to fabricate bistable memory device was extended to the methodology to realise a logic-gate device by stacking three distinct graphene-ferroelectric hybrid ribbons | - |
dc.language | English | - |
dc.publisher | INST ENGINEERING TECHNOLOGY-IET | - |
dc.title | Bistable memory and logic-gate devices fabricated by intercrossed stacking of graphene-ferroelectric hybrid ribbons | - |
dc.type | Article | - |
dc.identifier.wosid | 000380259600004 | - |
dc.identifier.scopusid | 2-s2.0-84978120474 | - |
dc.type.rims | ART | - |
dc.citation.volume | 11 | - |
dc.citation.issue | 7 | - |
dc.citation.beginningpage | 356 | - |
dc.citation.endingpage | 359 | - |
dc.citation.publicationname | MICRO & NANO LETTERS | - |
dc.identifier.doi | 10.1049/mnl.2016.0025 | - |
dc.contributor.localauthor | Lee, Hee Chul | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | graphene devices | - |
dc.subject.keywordAuthor | nanoribbons | - |
dc.subject.keywordAuthor | nanofabrication | - |
dc.subject.keywordAuthor | logic gates | - |
dc.subject.keywordAuthor | ferroelectric devices | - |
dc.subject.keywordAuthor | field effect transistors | - |
dc.subject.keywordAuthor | spin coating | - |
dc.subject.keywordAuthor | ferroelectric thin films | - |
dc.subject.keywordAuthor | semiconductor storage | - |
dc.subject.keywordAuthor | bistable memory device | - |
dc.subject.keywordAuthor | logic gate device | - |
dc.subject.keywordAuthor | intercrossed stacking | - |
dc.subject.keywordAuthor | graphene-ferroelectric hybrid ribbons | - |
dc.subject.keywordAuthor | ferroelectric gated graphene field effect transistor | - |
dc.subject.keywordAuthor | gate electrode | - |
dc.subject.keywordAuthor | ferroelectric polarisation | - |
dc.subject.keywordAuthor | C | - |
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