A 109 GHz CMOS Power Amplifier With 15.2 dBm Psat and 20.3 dB Gain in 65-nm CMOS Technology

Abstract

This letter presents a four-stage power amplifier (PA) with four-way transformer-based current combining using a standard 65 nm CMOS process. Each stage consists of common source (CS) topology with a capacitive cross-coupling neutralization to improve power gain, reverse isolation and AM-PM distortion. The power stage uses a diode connected NMOS transistor for linearity (AM-AM nonlinearity) enhancement. The proposed PA achieves a small-signal gain of 21 dB and 3-dB bandwidth of 17 GHz, output power of 12.5 dBm at a 1 dB compression point (OP1 dB) and a saturated output power of 15.2 dBm with a peak PAE of 10.3%. The total chip size including the pads and core chip size without the pads are 0.343 mm (2) and 0.103 mm (2), respectively