A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs

Abstract

A background timing-mismatch calibration algorithm is proposed, which detects and corrects the sampling time mismatches in time-interleaved analog-to-digital converter (ADC) channels by analyzing the sign-equality of a reference slope and a timing-mismatch-induced error value. The sign of the ideal derivative along the input is estimated through the adjacent channel outputs, thus not requiring an additional time-shifted ADC channel. The sign of the reference slope, which is the estimated sign of the ideal derivative at the sampling edge of the reference ADC, is matched against the sign of the error value to determine if the timing mismatch is leading or lagging the sampling edge of the reference ADC. The proposed algorithm aligns the sampling edge of each subchannel to that of the reference ADC by handling only two sign bits and thus reduces the timing mismatches with only negligible hardware overhead consisting of simple logic gates