A 1.1mW 32-thread Artificial Intelligence Processor with 3-level Transposition Table and On-chip PVT Compensation for Autonomous Mobile Robots
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Yoo, Hoi Jun | ko |
| dc.contributor.author | Kim, Youchang | ko |
| dc.contributor.author | Shin, Dongjoo | ko |
| dc.contributor.author | Lee, Jinsu | ko |
| dc.date.accessioned | 2016-07-07T05:55:32Z | - |
| dc.date.available | 2016-07-07T05:55:32Z | - |
| dc.date.created | 2016-06-22 | - |
| dc.date.created | 2016-06-22 | - |
| dc.date.created | 2016-06-22 | - |
| dc.date.issued | 2016-04 | - |
| dc.identifier.citation | IEEE Symposium on Low-Power and High-Speed Chips | - |
| dc.identifier.uri | http://hdl.handle.net/10203/209939 | - |
| dc.language | English | - |
| dc.publisher | IEEE | - |
| dc.title | A 1.1mW 32-thread Artificial Intelligence Processor with 3-level Transposition Table and On-chip PVT Compensation for Autonomous Mobile Robots | - |
| dc.type | Conference | - |
| dc.identifier.wosid | 000386772000002 | - |
| dc.identifier.scopusid | 2-s2.0-84982860684 | - |
| dc.type.rims | CONF | - |
| dc.citation.publicationname | IEEE Symposium on Low-Power and High-Speed Chips | - |
| dc.identifier.conferencecountry | JA | - |
| dc.identifier.conferencelocation | Yokohama Media & Communications Center | - |
| dc.contributor.localauthor | Yoo, Hoi Jun | - |
| dc.contributor.nonIdAuthor | Lee, Jinsu | - |
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